1. Field of the Invention
The invention relates generally to Field Programmable Gate Arrays and, more particularly, to embedded array structures to be incorporated within Field Programmable Gate Arrays.
2. Description of Prior Art
The concept of bitwrite for fixed memory arrays is well known in the industry. The bitwrite capability allows any number of select bits within a chosen memory word to be written, while other bits also accessed by this same address remain protected or masked and hence not written. Through this methodology a single memory address can be used to house status bits or other independently updated nibbles. Typically, the bitwrite capability has been included in compilable arrays for Application Specific Integrated Circuits (ASICs) using unique bitwrite lines for each bit in the stored word.
In the early 1980s the development of a new class of circuits called Field Programmable Gate Arrays (FPGAs) had begun. An FPGA is a chip, constructed of an array of general use uncommitted logic cells whose function and connectivity is user determined. Today, FPGAs are commonly known in the art, their common configurations include Look Up Tables (LUT), cell based, and the Programmable Logic Array (PLA) architectures. FPGAs combine the logic implementation capability, available in ASIC systems with the programmability features of PLAs. In many cases this programmability is non-destructive, and in some cases reconfiguration can occur on-the-fly without affecting the logic function of the chip as a whole.
With the development of FPGAs and their subsequent density growth beyond 10,000 gates, the need for on-chip reconfigurable memory resource has increased, paralleling the growth of memory requirements in ASIC products. A Field Programmable Memory Array (FPMA), addressing these needs and allowing memory use as Random Access Memory (RAM), Read Only Memory (ROM), Last In First Out (LIFO), First In First Out (FIFO), LUT, or register array with on-the-fly reconfiguration capability, has been described in a commonly owned U.S. Pat. No. 5,914,906.
U.S. Pat. No. 4,870,302 disclosed the Static Random Access Memory (SRAM) Cell-based FPGA architectures and on-the-fly reconfiguration capability within an FPGA.
Additionally, a commonly owned U.S. Pat. No. 5,914,906 describes the means for providing a flexible storage array system within an FPGA to provide a variety of memory related functions such as RAM, ROM, LIFO, FIFO, and cache. U.S. Pat. No. 5,802,003 discloses the means for initialization of array bit widths wider than the FPGA's configuration data bus. U.S. Pat. No. 5,646,544 details an FPGA cell architecture in which the cell's logic function is controlled by an array of configuration words. In that array, each configuration word is updatable on the fly from the configuration state machine and the configuration word of the larger set of configuration words chosen to program the cell is selectable from an independent source.
The FPMA architecture, comprising a block of uncommitted specialized cells within an FPGA optimized for generation of memory/data storage functions, provides for a number of subarrays. A subarray is an (M word).times.(N bit) block of specialized cells capable of being configured as a one or two port RAM, register or other special memory functions. Each subarray can function as a stand alone array in any of the above modes, or can be combined with one or more other subarrays to form a taller or wider functional macro. The FPMA can be reconfigured for different usages on-the-fly. Since each subarray is required to operate in a stand-alone mode, routing resources in the FPGA surrounding the FPMA need to be robust enough to support all address, data, and control lines coming into or out of all subarrays of the FPMA, while maintaining enough resource to support logic wiring near or over the FPMA.
The resulting routing burden is large enough to force functional limitations on the FPMA. One such limitation is that from a routing perspective, the bitwrite, as implemented in ASIC compilable arrays was too expensive. As a result a much simpler bytewrite capability in which two bytewrite lines controlled the masking of the upper and lower half of the word was adopted. Thus, for an 18 bits per word implementation shown in FIG. 1, each bytewrite line 150, 155 controls the masking of 9 bits/ memory cells in parallel. While allowing a basic masking function and greatly reducing routing congestion around the FPMA, the functional flexibility of FPMA implemented arrays is significantly reduced.
a routing selection matrix that is provided to wire the FPMA bytewrite signals to the FPGA logic controlling them, and possibly to other subarrays within the FPMA block are omitted from FIGS. 1-4. Although the reduction of the routing resource required to make this connection for a given function level is advantageous, the exact type of a resource used to make the connection is not critical to the invention.
As shown in FIG. 1, the prior art FPMA system 100 comprises a set of writehead multiplexers 10 of a width equal to the width of an array word 110 comprising memory cells 115 and controlled in parallel to select one of a number of hierarchical data bitlines and programming bitlines 20, and receiving alternate control by a reset line 30 common to all writeheads. In addition to the multiplexing function of the writehead 10, true and compliment versions of the data to be written to the cell 115 are generated and the cell may be set or reset depending on which of the two write port lines 120, 125 is active low when the word line 140 is pulsed. The two byte write lines 130, 135 are anded with the true and compliment data for their respective bytes such that a true 130 or compliment 135 line only goes low if byte write is active. If neither line 130, 135 goes low, and the word line 140 is pulsed, the cell 115 retains its value. Although alternate implementations could be achieved at the cell level, all implementations are based upon gating data into the cell 115 based upon a bytewrite signal on lines 130, 135 and a wordline signal on line 140.
Thus, it would be highly desirable to provide an FPMA having a bitwrite capability that both minimizes routing requirements external to the FPMA and significantly improves both bitwrite flexibility and scalability of the system while allowing on-the-fly reconfiguration in concert with the other functions of the FPMA. The invention has applicability to the incorporation of additional functions into Application Specific Integrated Circuit based arrays